The automotive industry is at the cusp of transformation. Features like connectivity, electrification, advanced driver assistance technologies like affordable cameras, radars, etc., are paving the way for autonomous driving. However, these automotive trends have made Integrated Circuits, System-On-Chips, ECUs significantly more complex and they now include multiple processors, DSPs, ASICs, FPGAs, peripherals, etc.
To accompany the complex hardware, a variety of modern software is employed on these devices. Conventionally, the different functions are developed independently in a pipelined supply chain, i.e., a well-defined process from architecture design, hardware development, manufacturing, software development to deployment.
As these systems have grown in complexity, today’s engineers face difficulties defining systems, developing and integrating hardware and software, and deploying such systems. In addition to the growing complexity, the market also expects new systems to be delivered at a much faster pace.
The increasing complexities and reduced TAT(Turn Around Time) have given rise to major challenges – Implementing new solutions quickly and maintaining such complex systems. These two challenges can be addressed by implementing Virtual Platforms.
What is a Virtual Platform?
A Virtual Platform (VP) is a behavioral twin of a hardware system that is simulated on a host computer and can execute the software very accurately. This technology can model many things from basic hardware with only a processor and memory, to a complete system made up of complex peripherals, boards, and interconnects. A VP is built using SystemC and TLM standards. SystemC, a special library of C++, creates an illusion of parallel processes of multiple electrical activities happening simultaneously just as it is in real hardware. TLM (Transaction Level Modeling) defines the methods to communicate between hardware components. Also, it defines standard interfaces for SystemC models which eases the integration of a system with several IPs and makes the simulation faster. VP models most of the features of real embedded systems such as buses, clocks, pipelines, memory, registers, interconnects, instruction sets, and interrupts.
A VP can be developed at different abstraction levels – behavioral models (functionally accurate), timed models (meets timing constraints), cycle-accurate models (clock cycle-accurate). The use cases of these models depend on the abstraction level of the model. The simulation speed will depend on the abstraction level; simulation speed will be fast for models which are abstracted at function level and speed will be significantly lesser for cycle-accurate models.
Use cases of Virtual Platform:
Hardware test case development:
The functionality of IC/ASICs can be modeled at desired abstraction level (preferably timed model). These virtual ICs can be used to develop hardware test cases before the silicon arrives. Once it arrives, these tests can be used to validate real hardware, thereby reducing the lead time of hardware validation.
Timed or cycle approximate VP models of MCU from various SOC vendors can be taken and integrated with their own IC/ASIC to form a complete virtual ECU. This will enable the development, validation, debugging at the system level and makes the maintenance easier.
VP enables engineers to define a system architecture using cycle-accurate models, which provides efficiency and performance for the desired application. They can choose IPs from different vendors, integrate them, to form the complete system. The resulting models can be used to measure the run time of software and benchmark the core/MCU for their software application. Timing and performance analysis can be done to check whether the defined architecture meets the requirements using simulation. Thus, the performance of the software on the new hardware can be gauged before the actual hardware arrives. They could even fine-tune the architecture to meet their goals before the actual hardware is in place and reduce any potential bottlenecks that could occur at any stage.
VP can be used to develop new software before the actual silicon board or RTL platform. The VP runs binaries of the software that will finally run on the actual hardware. Such software includes firmware, boot loaders, Bare-metal applications, AUTOSAR, compatible software, Linux, etc. A suitable way to run Bare-Metal software would be a timed model, as the models are accurate at the register level. Similarly, the timed model would also be suitable for an AUTOSAR-based software as the models would meet the timing requirements at the MCAL levels. On the other hand, function accurate models would be sufficient for running Linux applications.
A VP can be developed phase by phase and the software development team can acquire the functionalities based on their needs at any stage.
Software performance Analysis:
Development software can be run on timed or cycle approximate models and analyze the effect on various aspects like run time, hardware usage, bus transactions, busload, cache usage, etc. So, the software performance can be analyzed using VP and it can be still utilized even after hardware availability.
VP enables engineers to develop and validate hardware/software simultaneously. Based on abstraction levels and the need for simulation speed, a lot of flexibility can be used for different purposes. Potentially, the above-mentioned techniques can be further utilized to define and develop many complex systems for AI, IoT, Automated Driving, etc. Through VPs, product development time can be decreased by a few months. This, in turn, decreases time to market and increases the quality.
|Mr. Thalavai Venkatesan, Head of Sales and Key Account Management, Continental Automotive India|